View AD5930-15_8113569.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

programmable frequency sweep and output burst waveform generator data sheet ad5930 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005C2012 analog devices, inc. all rights reserved. features programmable frequency profile no external components necessary output frequency up to 25 mhz burst and listen capability preprogrammable frequency profile minimizes number of dsp/controller writes sinusoidal/triangular/square wave outputs automatic or single pin control of frequency stepping waveform starts at known phase increments at 0 phase or phase continuously power-down mode: 20 a power supply: 2.3 v to 5.5 v automotive temperature range: ?40c to +125c 20-lead pb-free tssop applications frequency sweeping/radar network/impedance measurements incremental frequency stimulus sensory applications proximity and motion bfsk frequency bursting/pulse trains general description the ad5930 1 is a waveform generator with programmable frequency sweep and output burst capability. utilizing embedded digital processing that allows enhanced frequency control, the device generates synthesized analog or digital frequency-stepped waveforms. because frequency profiles are preprogrammed, continuous write cycles are eliminated and thereby free up valuable dsp/controller resources. waveforms start from a known phase and are incremented phase continuously, which allows phase shifts to be easily determined. consuming only 8 ma, the ad5930 provides a convenient low power solution to waveform generation. the ad5930 can be operated in a variety of modes. in continuous output mode, the device outputs the required frequency for a defined length of time and then steps to the next frequency. the length of time the device outputs a particular frequency is either preprogrammed and the device increments the frequency automatically, or, alternatively, is incremented externally via the ctrl pin. in burst mode, the device outputs its frequency for a length of time and then returns to midscale for a further predefined length of time before stepping to the next frequency. when the msbout pin is enabled, a digital output is generated. (continued on page 3) functional block diagram control register data 24 incr sync and control syncout dgnd o/p msbout ioutb iout comp mclk ctrl increment controller frequency controller serial interface output burst controller interrupt ad5930 standby dvdd cap/2.5v dgnd a gnd a v dd ref fsadjust 24-bit pipelined dds core data data sync buffer buffer 10-bit dac fsync sclk sdata full-scale control on-board reference regulator vcc 2.5v 05333-001 figure 1. 1 protected by us patent number 6747583.
ad5930 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 4 timing characteristics ..................................................................... 6 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 terminology .................................................................................... 15 theory of operation ...................................................................... 16 the frequency profile ................................................................ 16 output modes ............................................................................. 16 serial interface ............................................................................ 17 powering up the ad5930 .......................................................... 17 programming the ad5930 ........................................................ 17 setting up the frequency sweep ............................................... 19 activating and controlling the sweep ..................................... 20 outputs from the ad5930 ........................................................ 21 applications ..................................................................................... 22 grounding and layout .............................................................. 22 ad5930 to adsp-21 01 interface ............................................. 22 ad5930 to 68hc11/68l11 interface ....................................... 23 ad5930 to 80c51/80l51 interface .......................................... 23 ad5930 to dsp56002 interface ............................................... 23 evaluation board ........................................................................ 24 schematic..................................................................................... 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 7/12rev. a to rev. b change to ordering guide ............................................................ 27 2/12rev. 0 to rev. a change to figure 2 ........................................................................... 5 changes to figure 22, figure 23, figure 24, figure 25, and figure 26 ................................................................................... 13 changes to figure 27, figure 28, figure 29, and figure 30 .......................................................................................... 25 11/05revision 0: initial version
data sheet ad5930 rev. | page 3 of 28 general description (continued from page 1) to program the device, the user enters the start frequency, the increment step size, the number of increments to be made , and the time interval that the part outputs each frequency. the frequency sweep profile is initiated, started , and executed by toggling the ctrl pin. a number of different sweep profiles are offered. frequencies can be stepped in triangular - sweep mode, which continuously sweeps up and down through the f requency range. alternatively, i n saw - sweep mode , the frequency is swept up through the frequency range, but return s to the initial frequency before executing the sweep again. in addition, a single frequency or burst can be generated without any sweep. the ad5930 is written to via a 3 - wire serial interface, which operates at clock rates up to 40 mhz. the device operates with a power supply from 2.3 v to 5.5 v . n ote tha t av dd and dv dd are independent of each other and can be operated from different voltages . the ad5930 also has a standby function, which allows sections of the device that are not being used to be powered down. the ad5930 is available in a 20 - lead pb - free tssop package . b
ad5930 data sheet rev. | page 4 of 28 specifications av dd = dv dd = 2.3 v to 5.5 v, agnd = dgnd = 0 v , t a = t min to t max , r set = 6.8 k?, r load = 200 ? for iout and ioutb, unless otherwise noted. table 1. y grade 1 parameter min typ max unit test conditions/comments signal dac specifications resolution 10 bits update rate 50 msps i out full -s cale 2 3 4.0 ma v out peak -to -p eak 0.56 v v out o ffset 45 mv f rom 0 v to the trough of the waveform v midscale 0.325 v voltage at midscale output output compliance 0.8 v av dd = 2.3 v, i nternal reference used 3 dc accuracy integral nonlinearity (inl) 1 .5 lsb differential n onlinearity (dnl) 0. 7 5 lsb dds specifications dynamic specifications signal -to - noise ratio 53 60 db f mclk = 50 mhz, f out = f mclk /4096 total harmonic distortion ?6 0 ?5 3 dbc f mclk = 50 mhz, f out = f mclk /4096 spu rious - free dynamic range (sfdr) wideband (0 to nyquist) ?6 2 ?5 2 dbc f mclk = 50 mhz, f out = f mclk /50 narrowband ( 200 khz) ?7 6 ? 73 dbc f mclk = 50 mhz, f out = f mclk /50 clock feedthrough ?50 dbc up to 16 mhz out wake -u p time 1.7 ms f rom s tandby output buffer v out peak -to -p eak 0 dv dd v typically, s quare wave on msb out and sync o ut output rise/fall time 2 12 ns voltage reference internal reference 1.15 1.18 1.26 v external refere nce range 1.3 v refout input impedance 1 k? v in @ ref pin < internal v ref 25 k? v in @ ref pin > internal v ref reference tc 2 90 ppm/c logic inputs input c urrent 0.1 1 a v inh , input high voltage 1.7 v dv dd = 2.3 v to 2.7 v 2.0 v dv dd = 2.7 v to 3.6 v 2.8 v dv dd = 4.5 v to 5.5 v v inl , input low voltage 0.6 v dv dd = 2.3 v to 2.7 v 0.7 v dv dd = 2.7 v to 3.6 v 0.8 v dv dd = 4.5 v to 5.5 v c in , input capacitance 2 3 pf logic outputs 2 v oh , output high voltage dv dd ? 0. 4 v v i sink = 1 ma v ol , output low voltage 0.4 v i sink = 1 ma floating - state o/ p capacitance 5 pf b
data sheet ad5930 rev. | page 5 of 28 y grade 1 parameter min typ max unit test conditions/comments power requirements f mclk = 50 mhz, f out = f mclk /7 av dd /dv dd 2.3 5.5 v i aa 3.8 4 ma i dd 2.4 2.7 ma i aa + i dd 6.2 6.7 ma low power sleep mode de vice is reset b efore putting into standby 20 85 a all outputs powered down, mclk = 0 v , serial interface active 140 240 a all outputs powered down, mclk active , serial interface active 1 operating temperature range is as follows: y version: ?40c to +125c; typical specifications are at 25c. 2 guaranteed by design. 3 minimum r set = 3.9 k ?. 10-bit dac on-board reference sin rom a vdd regul at or fsadjust 20pf 10nf 10nf r load 200? r set 6.8v refout com p iout full-scale contro l ad5930 cap/2.5v 12 100nf 05333-002 figure 2 . test circuit u sed to t est the specifications b
ad5930 data sheet rev. | page 6 of 28 timing characteristi cs all input signal s are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 to figure 7 . dv dd = 2.3 v to 5.5 v, agnd = dgnd = 0 v, a ll specifications t min to t max , unless otherwise noted. table 2. 1 parameter limit at t min , t max unit conditions/comments t 1 20 ns min mclk p eriod t 2 8 ns min mcl k high d uration t 3 8 ns min mclk low d uration t 4 25 ns min sclk p eriod t 5 10 ns min sclk high time t 6 10 ns min sclk low time t 7 5 ns min fsync to sclk falling edge setup t ime t 8 10 ns min fsync to sclk h old t ime t 9 5 ns min data setup t ime t 10 3 n s min data hold time t 11 2 x t 1 ns min minimum ctrl pulse width t 12 0 ns min ctrl rising edge to m clk falling edge setup time t 13 10 x t 1 ns typ ctrl rising edge to iout/ioutb delay (i nitial pulse, includes initialization ) 8 x t 1 ns typ ctrl ri sing ed ge to iout/ioutb delay (i nitial pulse, includes initialization ) t 14 2 x t 1 ns typ frequency change to sync output, saw sweep, each frequency increment t 15 2 x t 1 ns typ frequency change to sync output, saw sweep, end of sweep t 16 2 x t 1 ns typ frequency change to sync output, triangle sweep, end of sweep t 17 20 ns max mclk falling edge after 16 th clock edge to msb out 1 guaranteed by design, not production tested . mclk t 3 t 2 t 1 05333-003 figure 3 . master clock sclk fsync sdat a d15 d14 d2 d1 d0 d15 d14 t 7 t 9 t 6 t 8 t 10 t 5 t 4 05333-004 figure 4 . serial timing b
data sheet ad5930 rev. | page 7 of 28 mclk ctr l iout/ioutb t 12 t 11 t 13 05333-005 figure 5 . ctrl timing ctr l iout sync o/ p (each frequency increment) sync o/ p (end of sweep) t 13 t 15 t 14 05333-006 figure 6 . ctrl timing, saw -s weep mode ctr l iout sync o/ p (each frequency increment) sync o/ p (end of sweep) t 13 t 14 t 16 05333-007 figure 7 . ctrl timing, triangular -s weep mode b
ad5930 data sheet rev. | page 8 of 28 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 3. parameter rating av dd to agnd ?0.3 v to +6 .0 v dvdd to dgnd ?0.3 v to +6 .0 v agnd to dgnd ?0.3 v to +0.3 v cap/2.5 v to dgnd ?0.3 v to 2.75 v digital i/o voltage to dgnd ? 0.3 v to dv dd + 0.3 v analog i/o voltage to agnd ? 0.3 v to av dd + 0.3 v operating temperature range automoti ve (y v ersion) ?40c to +1 25c storage temperature r ange ?65c to +150c maximum junction temperature +150c tssop package (4 - layer b oard) ja thermal impedance 112 c/w jc thermal impedance 27.6 c/w reflow soldering (pb -f ree) 300c peak temperatur e 260(+0/?5)c time at peak te mperature 10 s ec to 40 s ec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condit ions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. elec trostatic charges as high a s 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high en ergy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. b
data sheet ad5930 rev. | page 9 of 28 pin configuration a nd function descriptions 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ref com p a vdd dgnd cap/2.5v dvdd fsadjust iout agnd st andb y sdat a sclk fsync msbout syncout mclk dgnd o/ p interrupt ctr l ioutb ad5930 top view (not to scale) 05333-008 figure 8 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 fsadjust full - scale adjust control. a resistor (rset) must be connected externally between this pin and agnd. this determines the magnitude of the full - scale dac current. the relationship between r set and the full - scale current is : iout full - scale = 18 v refout / r set where v refout = 1.20 v nominal and r set = 6.8 k ? typical . 2 ref voltage reference. this pin can be an input or an output. the ad5930 has an internal 1.18 v refer ence, which is made available at this pin. alternatively, this reference can be overdriven by an external reference, with a voltage range as given in the specifications section . a 10 nf decoupling capacitor shoul d be connected between ref and agnd. 3 comp dac bi as pin. this pin is used for decoupling the dac bias voltage to avdd. 4 avdd positive power supply f or the analog section . avdd can have a value from +2.3 v to +5.5 v. a 0.1 f decoupling capacitor should be connected between avdd and agnd. 5 dvdd positive power supply for the digital section. dvdd can have a value from +2.3 v to +5.5 v. a 0.1 f decoupling capacitor should be connected between dvdd and dgnd. 6 cap/2.5v digital circuitry. opera tes from a 2.5 v power s upply. this 2.5 v is generated from dv dd using an on - board regulator. the regulator requires a de coupling capacitor of typically 100 nf , which is connected from cap/2.5 v to dgnd. if dvdd is equal to or less than 2.7 v, cap/2.5 v can be short ed to dvdd. 7 dgnd ground for all digital circuitry . this excludes digital output buffers . 8 mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. the output frequency accuracy and phase noise are determined by this clock. 9 syncout digital output for sweep status information. user selectable for end of sweep (eos) or frequency increments through the control register (syncop bit). this pin must be enabled by settin g control r egister bit sy ncopen t o 1. 10 msb out digital output. the inverted msb of the dac data is available at this pin. this output pin must be enabled by setting bit msbout en in the control register to 1. 11 dgnd o/p separate dgnd connection for digital output buffers. connect to dgnd. 12 inte rrupt digital input. this pins acts as an interrupt during a frequency sweep. a low to h igh transition is sampled by the internal mclk, which resets internal state machines. this results in the dac output going to midscale. 13 ctrl digita l input. triple function pin for initialization, start , and external frequency increments. a low - to - high transition, sampled by the internal mclk, is used to initialize and start internal state machines, which then execute the pre - programmed fre quency swee p sequence. when in a uto -i ncrement mode, a single pulse executes the entire sweep sequence . when in e xternal i ncrement mode, each frequency increment is triggered by low -to - high transitions. 14 sdata serial data input. the 16 - bit serial data - word is appl ied to this input with the register address first followed by the msb to lsb of the data. 15 sclk serial clock input. data is clocked into the ad 5930 on each falling sclk edge. 16 fsync active low control input. this is the frame synchronization signal for the serial data. when fsync is taken low, the internal logic is informed that a new word is being loaded into the device. 17 standby active high digital input. when this pin is high, the internal mclk is disabled, and the reference dac and regulator are powered down. for optimum power saving, it is recommended to reset the ad5930 before putting it into standby , as t his results in a shutdown current of typically 20 a. b
ad5930 data sheet rev. | page 10 of 28 pin no. mnemonic description 18 agnd ground for all analog circuitry. 19 iout current output. this is a high impedance current source output. a load resistor of nominally 200 ? should be connected between iout and agnd. a 20 pf capacitor to agnd is also recommended to act as a low - pass filter and to reduce clock feedthrough. in conjunction with ioutb, a differential signal is available. 20 ioutb current output. ioutb is the co mpliment of iout. this pin should preferably be tied through an external load resistor of 200 ? to agnd , but can be tied directly to agnd. a 20 pf capacitor to agnd is also reco mmended as a low - pass filter to reduce clock feedthrough. in conjunction with i out, a differential signal is available. b
data sheet ad5930 rev. | page 11 of 28 typical performance characteristics mclk frequency (mhz) 9 8 7 6 4 3 5 2 1 0 0 504540353025201510 5 05333-027 i dd (ma) t a = 25c a vdd = 5v msbout , syncout enabled dvdd = 5v dvdd = 5 v , f out = mclk/7 dvdd = 3 v , f out = mclk/7 dvdd = 3v figure 9. current consumption (i dd ) vs. mclk f requency f out (hz) 7 6 4 3 5 2 1 0 25mhz 20mhz 15mhz 10mhz 5mhz 2mhz 1mhz 500khz 100khz 10khz 1khz 500khz 05333-028 i dd (ma) t a = 25 c mclk = 50mhz msbout on, syncout on msbout of f, syncout off msbout on, syncout off msbout of f, syncout on figure 10 . i dd vs. f out for various digital output c onditions legend 1. sine wa ve outpu t , internal ly controlled swee p 2. triangular outpu t , internal ly controlled swee p 3. sine wa ve outpu t , external ly controlled swee p 4. triangular outpu t , external ly controlled swee p control option (see legend) 3.5 3.0 2.0 1.5 2.5 1.0 0.5 0 3 4 2 1 05333-029 i dd (ma) aidd didd figure 11 . i dd vs . output waveform type and c ontrol mclk frequency (mhz) ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 504540 353025201510 5 05333-030 sfdr (dbc) a vdd = dvdd = 3v/5v mclk = 50mhz c reg = 0 11 1 111 1 111 1 t a = 25c f out = mclk/7 f out = mclk/50 f out = mclk/3 figure 12 . wideband sfdr vs . mclk frequency mclk frequency (mhz) ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 504540353025201510 5 05333-031 sfdr (dbc) a vdd = dvdd = 3v/5v mclk = 50mhz c reg = 0 11 1 111 1 111 1 t a = 25c f out = mclk/7 f out = mclk/50 f out = mclk/3 figure 13 . narrowband sfdr vs . mclk frequency f out (mhz) ?30 ?40 ?50 ?60 ?70 ?80 ?90 0.001 100 10 1 0.1 0.01 05333-032 sfdr (dbc) a vdd = dvdd = 3v/5v c reg = 0 11 1 111 1 111 1 t a = 25c mclk = 1mhz mclk = 10mhz mclk = 30mhz mclk = 50mhz figure 14 . wideband sfdr vs . f out for various mclk frequencies b
ad5930 data sheet rev. | page 12 of 28 mclk frequency (mhz) 70 65 60 55 50 45 40 50m 40m 30m 20m 10m 0 05333-034 snr (db) t a = 25c a vdd = dvdd = 5v f out = fmclk/4096 figure 15 . snr vs . mclk f requency temperature (c) 1.25 1.23 1.21 1.19 1.17 1.15 120 100 80604020 0 ?40 ?20 05333-035 v ref (v) a vdd = dvdd = 5v figure 16 . v ref vs. temperature temperature (c) 2.0 1.8 1.9 1.7 1.6 1.5 1.3 1.4 1.2 120 100 80604020 0 ?40 ?20 05333-036 wake-up time (ms) a vdd = dvdd = 5v a vdd = dvdd = 2.3v figure 17 . wake -u p time vs. temperature v out peak-to-peak (mv) 12 10 8 6 2 4 0 552 572 568 570 566564562560558556554 05333-025 number of devices figure 18 . histogram of v out peak - to -p eak v out offset (mv) 12 10 8 6 2 4 0 44.4 46.2 45.8 46.0 45.6 45.4 45.2 45.0 44.8 44.6 05333-026 number of devices figure 19 . histogram of v out offset modulating frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?70 ?60 ?80 10 1m 100k 10k 1k 100 05333-033 attenuation (db) t a = 25c 100mv p-p ripple no decoupling on supplies a vdd = dvdd = 5v a vdd (on iout) dvdd (on cap/2.5v) figure 20 . pssr b
data sheet ad5930 rev. | page 13 of 28 f (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100k 10k 1k 100 05333-037 phase noise figure 21 . output phase noise 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 100k 05333-014 (db) vwb 30 rwb 100 st 100 sec frequency (hz) figure 22 . f mclk = 10 mhz; f out = 2 .4 khz, frequency word = 000fba 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 5m 05333-015 (db) vwb 300 rwb 1k st 50 sec frequency (hz) figure 23 . f mclk = 10 mhz; f out = 1.43 mhz = f mclk /7, frequency word = 249249 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 5m 05333-016 (db) vwb 300 rwb 1k st 50 sec frequency (hz) figure 24 . f mclk = 10 mhz; f out = 3.33 mhz = f mclk /3, frequency word = 555555 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 160k 05333-017 (db) vwb 30 rwb 100 st 200 sec frequency (hz) figure 25 . f mclk = 50 mh z; f out = 12 khz, frequency word = 000fba 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 1.6m 05333-018 (db) vwb 300 rwb 100 st 200 sec frequency (hz) figure 26 . f mclk = 50 mhz; f out = 1 20 khz, frequency word = 009d49 b
ad5930 data sheet rev. | page 14 of 28 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05333-019 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 27 . f mclk = 50 mhz; f out = 1 .2 mhz, frequency word = 0624dd 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05333-020 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 28 . f mclk = 50 mhz; f out = 4 .8 mhz, frequency word = 189374 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05333-021 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 29 . f mclk = 50 mhz; f out = 7.143 mhz = f mclk /7, frequency word = 2492492 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05333-022 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 30 . f mclk = 50 mhz; f out = 16.667 mhz = f mclk /3, frequency word = 5555555 b
data sheet ad5930 rev. | page 15 of 28 terminology integral nonlinearity (inl) this is the maximum deviation of any code from a straight line passing thro ugh the endpoints of the transfer function. the endpoints of the tr ansfer function are zero scale and full scale . the error is expressed in lsbs. differential nonlinearity (dnl) this is the difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. output compliance the output compliance refers to the maximum voltage that can be generated at the output of the dac to meet the specifica - tions. when voltages greater than that specified for the output compliance are generated, the ad5930 may not meet the specifications listed in the data sheet. spurious - free dynamic range (sfdr) along with the frequency of interest, harmonics of the fundamental freque ncy and images of these frequencies are present at the output of a dds device. the sfdr refers to the largest spur or harmonic that is present in the band of interest. the wide band sfdr gives the magnitude of the largest harmonic or spur relative to the m agnitude of the fundamental frequency in the 0 to nyquist bandwidth. the narrow band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz about the fundamental frequency. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the rms value of the fundamental . fo r the ad5930, thd is defined as 1 6 54 32 v vvvvv thd 22222 log20) db ( ++++ = w here : v 1 is the rms amplitude of the fundamental . v 2 , v 3 , v 4 , v 5 , and v 6 are the rms ampl itudes of the second through th e sixth harmo nic. signal -to - noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency. the value for snr is expressed in decibels. clock feedthrough there is feedthroug h from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the ad5930s output spectrum. b
ad5930 data sheet rev. | page 16 of 28 theory of operation the ad5930 is a general - purpose synthesized waveform gen erator capable of providing digitally programmable waveform sequences in both the frequency and time domain. the device contains embedded digital processing to provi de a repetitive sweep of a user programmable frequency profile allowing enhanced frequency control. because the device is pre - programmable, it eliminates continuous write cycles from a dsp/ controller in generating a particular waveform. the frequency profil e the frequency profile is defined by the start frequency (f start ), the frequency i ncrement (f) and the number of increments per sweep (n incr ). the increment interval between frequency increments, t int , is eith er user programmable w ith the interval automatically determined by the device (auto - increment mode) , or externally controlled via a hardw are pin (external increment mode) . for automatic update, the interval profile can either be fo r a fixed number of clock periods or for a fixed number of output waveform cycles. in the auto - increment mode, a single pulse at the ctrl pin starts and executes the f requency sweep. in the external increment mode, the ctrl pin also starts the sweep , but t he frequency increment interval is determined by the tim e interval between sequential 0 /1 transitions on the ctrl pin. furthermore, the ctrl pin can be used to directly control the burst profile, where during the input high time, the output waveform is present, and during the input low time , the output is reset to midscale. the frequency profile can be swept in two different modes: saw sweep or triangular (up/down) sweep. saw - sweep mode in the case of a saw sweep, the ad5930 repeatedly sweeps between sweep start to sweep end , that is, from f start incrementally to f start + n incr f and then returns directly to f start t o begin again (see figure 31 ). this gives a saw - sweep cycle time of (n incr + 1) t int f st art f st art f st art + ?f f st art + n incr ?f midscale 05333-009 figure 31 . s aw - sweep profile triangular - sweep mode in the case of a triangular sweep, the ad5930 repeatedly sweeps between sweep start to sweep end, that is, from f start incrementally to f start + n incr f and then returns to f start in a decremented manner (see figure 32 ). the triangular - sweep cycle time is given by (1 + (2 n incr )) t int f st art 05333-010 f st art f st art f st art + ?f f st art + ?f f st art + n incr ?f midscale figure 32 . triangular - sweep profile output modes the ad5930 offers two possibl e output modes: continuous output mode and burst output mode. both of these modes are illustrated in figure 33. 05333-0 11 continuous mode burst mode 1 2 number ste p changes t int t burst figure 33 . continuous mode and burst mode of the ad5930 continuous output m ode in this mode, each frequency of the sweep is available for the length of time programmed into the time interval (t int ) register. this means the frequency swept output signal is continuously available, and is therefore phase continuous at all frequency increments. to set up the ad5930 in continuous mode, the cw/burst bit (d7) in the control register must be set to 0. see the activating and c ontrolling the sweep section f or more details. burst output m ode in this mode, the ad5930 provides a programmable burst of the waveform output for a fixed length of time (t burst ) within the programmed increment interval ( t int ). then for the remainder of the t int interval, the output is reset to mid - scale and remains there un til the next frequency increment. b
data sheet ad5930 rev. | page 17 of 28 this is beneficial for applications where the user needs to burst a frequency for a set period, and then listen for a response before increasing to the next frequency. note also that t he beginning of each frequency incre ment is at midscale (phase 0 rad ). t herefore , the phase of the signal is always known. to set up the ad5930 in burst mode, the cw/burst bit (d7) in the c ontrol register must be set to 1 . see the activating and c ontrolling the sweep section for more details about the burst output mode. serial interface the ad5930 has a standard 3 - wire serial interface, which is compatible with spi ? , qspi ? , microwire ?, and dsp interface standards. data is loaded into the device as a 1 6- bit word under the control of a serial clock input, sclk. the timing diagram for this operation is given in figure 4 . the fsync input is a level - triggered input that acts as a frame synchronization and chip enable. data can only be transferred into the device when fsync is low. to start the serial data transfer, fsync should be taken low, observing the minimum fsync to sclk falling edge setup time, t 7 . after fsync goes low, serial data is shifted into the device' s input shift register on the falling edges of sclk for 16 clock pulses. fsync can be taken high after the 16 th falling edge of sclk, observing the minimum sclk falling edge to fsync rising edge time, t 8 . alternatively, fsync can be kept low for a multiple of 16 sclk pulses, and then brought high at the end of the data transfer. in this way, a continuous stream of 16 - bit words can be loaded while fsync is held low. fsync should only go high after the 16th sclk falling edge of the last word is loaded. the s clk can be continuous , or, alternatively, the sclk can idle high or low between write operations. powering u p the ad5930 when the ad5930 is powered up, the part is in an un defined state, and therefore , must be reset before use. the eight registe rs (control and frequency) cont ain invalid data and need to be set to a known value by the user. the control register should be the first register to be programmed, as this sets up the part. note that a wri te to the control register automatically reset s the internal stat e machines and provide s an analog output of midscale as it provides the same function as the interrupt pin. typically, this is followed by a serial loading of all the required sweep parameters. the dac output remains at midscale until a sweep is started using the ctrl pin. programming the ad59 30 the ad5930 is designed to provide automatic frequency sweeps when the ctrl pin is triggered. the automatic sweep is controlled by a set of registers, the addresses of which are given in table 5 . the function of each register is described in more detai l in the following section. table 5 . register address es register address d15 d14 d13 d12 mnemonic name 0 0 0 0 c reg control bits 0 0 0 1 n incr nu mber of increments 0 0 1 0 ? f l ower 12 bits of delta frequency 0 0 1 1 ? f hi gher 12 bits of delta frequency 0 1 t int increment interval 1 0 t burst burst interva l 1 1 0 0 f start l ower 12 bits of start frequency 1 1 0 1 f start hi gher 12 bits of start frequency 1 1 1 0 reser ved 1 1 1 1 reserved the control register the ad5930 contains a 12 - bit control register (see tabl e 6 ) that sets up the operating modes of the ad5930. the different functions and the various output options from the ad5930 are controlled by this register. table 7 describes the individual bits of the control register. to address the control register, d15 to d12 of the 16 - bit serial word must be set to 0 . table 6 . control register d15 d14 d13 d12 d11 to d0 0 0 0 0 control bits b
ad5930 data sheet rev. | page 18 of 28 table 7 . description of bits in the control register bit name function d15 to d12 addr register address bits. d11 b24 two write operations are required to load a complete word into the f start register and the f register. when b24 = 1, a complete word is loaded into a frequency register in two consecutive writes. the first write contains the 12 lsbs of the frequency word and the next write contains the 12 msbs. refer to table 5 for the appropriate addresses. the write to the destination register occurs after both words have been loaded, so the register never holds an intermediate value. when b24 = 0, the 24 - bit f start /f register operates as two 12 - bit registers, one c ontaining the 12 msbs and the other containing the 12 lsbs. this means that the 12 msbs of the frequency word can be altered independent of the 12 lsbs and vice versa. this is useful if the complete 24 - bit update is not required. to alter the 12 msbs or the 12 lsbs, a single write is made to the appropriate register address. refer to table 5 for the appropriate addresses. d10 dac enable when dac enable = 1, the dac is enabled. when dac enable = 0, the dac is power ed down. this saves power and is beneficial when only using the msb of the dac input data (available at the msbout pin). d9 sine/tri the function of this bit is to control what is available at the iout/ioutb pins. when sine/tri = 1, the sin rom is used to convert the phase information into amplitude information resulting in a sinusoidal signal at the output. when sine/tri = 0, the sin rom is bypassed, resulting in a triangular (up - down) output from the dac. d8 msbouten when msbouten = 1, the msbout pin is enabled. when msbouten = 0, the msbout is disabled (tri - state). d7 cw/burst when cw/burst = 1, the ad5930 outputs each frequency continuously for the length of time or number of output waveform cycles specified in the appropriate register, t burst . when cw/burst = 0, the ad5930 bursts each frequency for the length of time/number of cycles specified in the burst register, t burst . for the remainder of the time within each increment window (t burst ? t int ), the ad5930 outputs a dc value of midscale. in external increment mode, it is defined by the pulse widths on the ctrl pin. d6 int/ext burst this bit is active when d7 = 0 and is also used in conjunction with d5. when the user is incrementing the frequency externally (d5 = 1), d6 dictates whether the user is controlling the burst internally or externally. when int/ext burst = 1, the output burst is controlled externally through the ctrl pin. this is useful if the user is using an external source t o both trigger the frequency increments and determine the burst interval. when int/ext burst = 0, the output burst is controlled internally. the burst is pre - programmed by the user into the t burst register (the burst interval can either be clock - based or f or a specified number of output cycles). when d5 = 0, this bit is ignored. d5 int/ext incr when int/ext incr = 1, the frequency increments are triggered externally through the ctrl pin. when int/ext incr = 0, the frequency increments are triggered automa tically. d4 mode the function of this bit is to control what type of frequency sweep is carried out. when mode = 1, the frequency profile is a saw sweep. when mode = 0, the frequency profile is a triangular (up - down) sweep. d3 syncsel this bit is acti ve when d2 = 1. it is user - selectable to pulse at the end of sweep (eos) or at each frequency increment. when syncsel = 1, the syncop pin outputs a high level at the end of the sweep and returns to zero at the start of the subsequent sweep. when syncsel= 0, the syncop outputs a pulse of 4 t clock only at each frequency increment. d2 syncouten when syncouten= 1, the sync output is available at the syncop pin. when syncouten= 0, the syncop pin is disabled (tri - state). d1 reserved this bit must always be set to 1. d0 reserved this bit must always be set to 1. b
data sheet ad5930 rev. | page 19 of 28 setting up the frequency sweep as stated previously in the frequency profile section, the ad5930 requires certain registers to be programmed to enable a frequency sweep. the following sections discuss these registers in more detail. start frequency (f start ) to start a frequency sweep, the user needs to tell the ad5930 what frequency to start sweeping from. this frequency is stored in a 24-bit register called f start . if the user wishes to alter the entire contents of the f start register, two consecutive writes must be performed, one to the lsbs and the other to the msbs. note that for an entire write to this register, the control bit b24 (d11) should be set to 1 with the lsbs programmed first. in some applications, the user does not need to alter all 24 bits of the f start register. by setting the control bit b24 (d11) to 0, the 24-bit register operates as two 12-bit registers, one containing the 12 msbs and the other containing the 12 lsbs. this means that the 12 msbs of the f start word can be altered independently of the 12 lsbs, and vice versa. the addresses of both the lsbs and the msbs of this register is given in table 8. table 8. f start register bits d15 d14 d13 d12 d11 to d0 1 1 0 0 12 lsbs of f start <110> 1 1 0 1 12 msbs of f start <2312> frequency increments ( f) the value in the f register sets the increment frequency for the sweep and is added incrementally to the current output frequency. note that the increment frequency can be positive or negative, thereby giving an increasing or decreasing frequency sweep. at the start of a sweep, the frequency contained in the f start register is output. next, the frequency (f start + f ) is output. this is followed by (f start + f + f) and so on. multiplying the f value by the number of increments (n incr ), and adding it to the start frequency (f start ), gives the final frequency in the sweep. mathematically this final frequency/stop frequency is represented by f start + (n incr f). the f register is a 23-bit register, and requires two 16-bit writes to be programmed. table 9 gives the addresses associated with both the msb and lsb registers of the f word. table 9. f register bits d15 d14 d13 d12 d11 d10 to d0 sweep direction 0 0 1 0 12 lsbs of f <110> n/a 0 0 1 1 0 11 msbs of f <2212> positive f (f start + f) 0 0 1 1 1 11 msbs of f <2212> negative ? f (f start ? f) number of increments (n incr ) an end frequency, or a maximum/minimum frequency before the sweep changes direction is not required on the ad5930. instead, this end frequency is calculated by multiplying the frequency increment value (f) by the number of frequency steps (n incr ), and adding it to/subtracting it from the start frequency (f start ), that is, f start + n incr f. the n incr register is a 12-bit register, with the address shown in table 10. table 10. n incr register bits d15 d14 d13 d12 d11 to d0 0 0 0 1 12 bits of n incr <110> the number of increments is programmed in binary fashion, with 000000000010 representing the minimum number of frequency increments (2 increments), and 111111111111 representing the maximum number of increments (4095). table 11. n incr data bits d11 d0 number of increments 0000 0000 0010 2 frequency increments. this is the minimum number of frequency increments. 0000 0000 0011 3 frequency increments. 0000 0000 0100 4 frequency increments. 1111 1111 1110 4094 frequency increments. 1111 1111 1111 4095 frequency increments. increment interval (t int ) the increment interval dictates the duration of the dac output signal for each individual frequency of the frequency sweep. the ad5930 offers the user two choices: ? the duration is a multiple of cycles of the output frequency. ? the duration is a multiple of mclk periods. this is selected by bit d13 in the t int register as shown in table 12. table 12. t int register bits d15 d14 d13 d12 d11 d10 to d0 0 1 0 x x 11 bits <100> fixed number of output waveform cycles. 0 1 1 x x 11 bits <100> fixed number of clock periods. programming of this register is in binary form with the minimum number being decimal 2. note in table 12 that 11 bits, bit d10 to bit d0, of the register are available to program the time interval. as an example, if mclk = 50 mhz, then each clock period/base interval is (1/50 mhz) = 20 ns. if each frequency needs to be output for 100 ns, then <00000000101> or decimal 5 needs to be programmed to this register. note that the ad5930 can output each frequency for a maximum duration of 211 ?1 (or 2047) times the increment interval. b
ad5930 data sheet rev. | page 20 of 28 therefore, in this example, a time interval of 20 ns 2047 = 40 s is the maximum, with the minimum being 40 ns. for some applications, this maximum time of 40 s may be insufficient. therefore, to cater for sweeps that need a longer increment interval, time-base multipliers are provided. bit d12 and bit d11 are dedicated to the time-base multipliers (see table 12). a more detailed table of the multiplier options is given in table 13. table 13. time-base multiplier values d12 d11 multiplier value 0 0 multiply (1/mclk) by 1 0 1 multiply (1/mclk) by 5 1 0 multiply (1/mclk) by 100 1 1 multiply (1/mclk) by 500 if mclk is 50 mhz and a multiplier of 500 is used, then the base interval (t base ) is now (1/(50 mhz) x 500)) = 10 s. using a multiplier of 500, the maximum increment interval is 10 s 2 11 ? 1 = 20.5 ms. therefore, the option of time-base multipliers gives the user enhanced flexibility when programming the length of the frequency window, because any frequency can be output for a minimum of 40 ns up to a maximum of 20.5 ms. length of sweep time the length of time to complete a user-programmed frequency sweep is given by the following equation: t sweep = (1 + n incr ) t base burst time resister (t burst ) as previously described in the burst output mode section, the ad5930 offers the user the ability to output each frequency in the sweep for a length of time within the increment interval (t int ), and then return to midscale for the remainder of the time (t int C t burst ) before stepping to the next frequency. the burst option must be enabled. this is done by setting bit d7 in the control register to 0. similar to the time interval register, the burst register can have its duration as: ? a multiple of cycles of the output frequency ? a multiple of mclk periods the address for this register is given in table 14. table 14. t burst register bits d15 d14 d13 d12 d11 d10 to d0 1 0 0 x x 11 bits of <010> fixed number of output waveform cycles. 1 0 1 x x 11 bits of <010> fixed number of clock periods. however, note that when using both the increment interval (t int ) and burst time register (t burst ), the settings for bit d13 should be the same. in instances where they differ, the ad5930 defaults to the value programmed into the t int register. similarly, bit 12 and bit 11, the time-base multiplier bits, always default to the value programmed into the t int register. activating and controlling the sweep after the registers have been programmed, a 0 1 transition on the ctrl pin starts the sweep. the sweep always starts from the frequency programmed into the f start register. it changes by the value in the ? f register and increases by the number of steps in the n incr register. however, both the time interval and burst duration of each frequency can be internally controlled using the t int and t burst registers, or externally using the ctrl pin. the options available are: 1. auto-increment, auto-burst control 2. external increment, auto-burst control 3. external increment, external burst control 1. auto-increment, auto-burst control the values in the t int and t burst registers are used to control the sweep. the ad5930 bursts each frequency for the length of time programmed in the t burst register, and outputs midscale for the remainder of the interval time (t int C t burst ). to set up the ad5930 to this mode, cw/burst (bit d7) in the control register must be set to 0, int/ext burst (bit d6) must be set to 0, and int/ext incr (bit d5) must be set to 0. note that if the part is only operating in continuous mode, then (bit d7) in the control register should be set to 1. 2. external increment, auto-burst control the time interval, t int , is set by the pulse rate on the ctrl pin. the first 0 1 transition on the pin starts the sweep. each subsequent 0 1 transition on the ctrl pin increments the output frequency by the value programmed into the ? f register. for each increment interval, the ad5930 outputs each frequency for the length of time programmed into the t burst register, and outputs midscale until the ctrl pin is pulsed again. note that for this mode, the values programmed into bit d13, bit d12, and bit d11 of the t burst register are used. b
data sheet ad5930 rev. | page 21 of 28 to setup the ad5930 to this mode, cw/burst ( bi t d7) in the c ontrol register must be set to 0 , int /ext burst ( bit d6) must be set to 0 , and int/ext incr ( bit d5) must be set to 1. note that if the part is only oper ating in continuous mode, then bit d7 in the control register should be set to 1. 3. extern al increment, external burst control: both the i ncrement i nterval ( t int ) and the b urst i nterval (t burst ) are controlled by the ctrl pin. a 0 1 transition on the ctrl pin starts the sweep. the duration of ctrl high then dictates the length of time the ad5 930 burst s that frequency. the low time of ctrl is the listen time , that is, how long the part remain s at midscale. bring ing the ctrl pin high again initiate s a frequency increment, and the pattern continues. for this mode, the settings for bit d13, bit d12 , and bit d11 are ignored. to setup the ad5930 to this mode, cw/burst ( bit d7) in the c ontrol register must be set to 0 , int /ext burst ( bit d6) must be set to 1 , and int/ext incr ( bit d5) must be set to 1 . note that if the part is only operating in con tinuous mode, then bit d7 in the con trol register should be set to 1 . interrupt pin this function is used as an interrupt dur ing a frequency sweep. a low - to - high transition on this pin is sampled by the internal mclk, thereby resetting internal state mach ines, which results in the output going to midscale. standby pin sections of the ad5930 that are not in use can be powered down to minimize power consumption. this is done by using the standby pin. for the optimum power savings, it is recommended to reset the ad5930 before entering standby, because doing so reduces the power - down current to 20 a. when this pin is high, the internal mclk is disabled, and the reference, dac, and regulator are powered down. when in this state, the dac output of the ad5930 remains at its present value as the nco is no longer accumulating. when the device is taken back out of standby mode, the mclk is re - activated and the sweep continues. to ensure correct operation for new data, it is recommended that the device be internally reset using a control register write or using the interrupt pin, and then restarted. outputs from the ad5 930 the ad5930 offers a variety of outputs from the chip. the analog outputs are available from the iout/ioutb pins, and include a sine wave and a triangle output. the digital out puts are available from the msb out pin and the syncout pin. analog outputs sinusoidal output the sin rom is used to convert the phase information from the frequency register into amplitude information, which results in a sinusoidal signal at the output. to have a sinusoidal output from the iout/ioutb pins, set bit sine/tri ( bit d9) to 1. triangle output the sin rom can be bypassed so that the truncated digital output from the nco is sent to the dac. in this case, the ou tput is no longer sinusoidal. the dac produces a 10 - bit linear triangular function. to have a triangle output from the iout/ioutb pins, set bit sine/tri (d9) to 0. note that the dac enable bit (d10) must be 1 (that is, the dac is enabled) when using these pins. v out max 3p/2 7p/2 p/2 5p/2 9p/2 1 1p/2 v out min 05333-012 figure 34 . triangle output digital outputs square wave output from msb out the inverse of the msb from the nco can be output from the ad5930. by setting the msbouten (d8) control bit to 1, the inverted msb of the d ac data i s available at the msb out pin. this is useful as a digital clock source. dvdd dgnd 05333-013 figure 35 . msb output syncout p in the syncout pin can be used to give the status of the sweep. it is user selectable for the en d of the sweep, or to output a 4 t clock pulse at frequency increments. the timing information for both of these modes is shown in figure 6 and figure 7 . the syncout pin must be enabled before use. t his is done using bit d2 in the control register. the output available from this pin is then controlled by bit d3 in the control register. see table 5 for more information. b
ad5930 data sheet rev. b | page 22 of 28 applications grounding and layout the printed circuit board that houses the ad5930 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad5930 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad5930. if the ad5930 is in a system where multiple devices require agnd to dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the ad5930. avoid running digital lines under the device as these couple noise onto the die. the analog ground plane should be allowed to run under the ad5930 to avoid noise coupling. the power supply lines to the ad5930 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the other side. good decoupling is important. the analog and digital supplies to the ad5930 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd, respectively, with 0.1 f ceramic capacitors in parallel with 10 f tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in systems where a common supply is used to drive both the avdd and dvdd of the ad5930, it is recommended that the systems avdd supply be used. this supply should have the recommended analog supply decoupling between the avdd pins of the ad5930 and agnd, and the recommended digital supply decoupling capacitors between the dvdd pins and dgnd. proper operation of the comparator requires good layout strategy. the strategy must minimize the parasitic capacitance between v in and the sign bit out pin by adding isolation using a ground plane. for example, in a multilayered board, the v in signal could be connected to the top layer and the sign bit out connected to the bottom layer, so that isolation is provided between the power and ground planes. interfacing to microprocessors the ad5930 has a standard serial interface that allows the part to interface directly with several microprocessors. the device uses an external serial clock to write the data/control information into the device. the serial clock can have a frequency of 40 mhz maximum. the serial clock can be continuous, or it can idle high or low between write operations. when data/control information is being written to the ad5930, fsync is taken low and is held low while the 16 bits of data are being written into the ad5930. the fsync signal frames the 16 bits of information being loaded into the ad5930. ad5930 to adsp-2101 interface figure 36 shows the serial interface between the ad5930 and the adsp-2101. the adsp-2101 should be set up to operate in the sport transmit alternate framing mode (tfsw = 1). the adsp-2101 is programmed through the sport control register and should be configured as follows: 1. internal clock operation (isclk = 1) 2. active low framing (invtfs = 1) 3. 16-bit word length (slen = 15) 4. internal frame sync signal (itfs = 1) 5. generate a frame sync for each write (tfsr = 1) transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the serial clock and clocked into the ad5930 on the sclk falling edge. ad5930 1 adsp-2101 1 1 additional pins omitted for clarity. tfs dt sclk fsync 05333-038 sdata sclk figure 36. adsp-2101 to ad5930 interface
data sheet ad5930 rev. | page 23 of 28 ad5930 to 68hc11/68l 11 interface figure 37 shows the serial interface between the ad5930 and the 68hc11/68l1 1 controller. the controller is configured as the master by s etting bit mstr in the spcr to 1, which provides a serial clock on sck while the mosi output drives the serial d ata line sdata. since the controller does not have a dedicated frame sync pin, the fsync signal is derived from a port line (pc7). the setup conditions for correct operation of the interface are as follows: 1. sck idles high betwe en write operations (cpol = 0) 2. data is valid on t he sck falling edge (cpha = 1) when data is being transmitted to the ad5930, the fsync line is taken low (pc7). serial data from the 68hc11/68l11 is tran smitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data into the ad5930, pc7 is held low after the first 8 bits are transferred and a second serial write operation is performed to the ad5930. only after the second 8 bits have been transferred should fsync be taken high again. ad5930 1 68hc 1 1/68l 11 1 1 additiona l pins omitted for clarit y. pc7 mosi sck fsync 05333-039 sdat a sclk figure 37 . 68hc11/68l11 to ad5930 interface ad5930 to 80c51/80l5 1 interface figure 38 shows the serial interface between the ad5930 and the 80c51/80l51 controller. the controller is operated in mode 0 so that txd of the 80c51/80l51 drives sclk of the ad5930, while rxd drives the serial data line sdata. the fsync signal is again derived from a bit programmable pin on the port (p3.3 being used in the diagram). when data is to be transmitted to the ad5930, p3.3 is taken low. the 80c51/80l51 transmits data in 8 - bit bytes, thus , only eight falling sclk edges occur in each cycle. to lo ad the remaining 8 bits to the ad5930, p3.3 is held low after the first 8 bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. p3.3 is taken high following the completion of the second write operation. sclk should idle high between the two write operations. the 80c51/80l51 outputs the serial data in a n lsb first format . the ad5930 accepts the msb first (the 4 msbs being the control information, the next 4 bits being the address while the 8 lsbs contain t he data when writing to a destination register). therefore, the transmit routine of the 80c51/80l51 must take this into account and rearrange the bits so that the msb is output first. ad5930 1 80c51/80l51 1 1 additiona l pins omitted for clarit y. p3.3 rxd txd fsync 05333-040 sdat a sclk figure 38 . 80c51/80l51 to ad5930 interface ad 5930 to dsp56002 int erface figure 39 shows the interface between the ad5930 and the dsp56002. the dsp56002 is configured for normal mode , asynchronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated internally (sc2 = 1), the transfers are 16 bits wide (wl1 = 1, wl0 = 0), and the frame sync signal frame s the 16 bits (fsl = 0). the frame sync signal is available on p in sc2, but needs to be inverted before being appli ed to the ad5930. the interface to the dsp56000/dsp56001 is similar to that of the dsp56002. ad5930 1 dsp56002 1 1 additiona l pins omitted for clarit y. sc2 std sck fsync 05333-041 sdat a sclk figure 39 . dsp56002 to ad5930 interface b
ad5930 data sheet rev. | page 24 of 28 evaluation board the ad5930 evaluation board allows designers to evaluate the high pe rformance ad5930 dds mod ulator with minimum effort. the evaluation board interfaces to the usb port of a pc. it is possible to power the entire board off the usb port. all that is needed to complete the evaluation of the chip is either a spectrum analyzer or a scope. the dds evaluation kit includes a populated and tested ad5930 printed circuit board. the e va l - ad5930eb kit is shipped with a cd - rom that includes self - installing software. the pc is connected to the evaluation board using the supplied cable. t he software is compatible w ith microsoft? windows? 2000 and windows xp . a schematic of the evaluation board is shown in fig ure 40 and figure 41 . using the ad 5930 evaluatio n board the ad 5930 evaluation kit is a test system designed to simplify the evaluation of the ad 5930 . an application note is also available with the evaluation board and gives full information on operating the evaluation board. prototyping area an area is available on the evaluation board for the user to add additional circuits to the evaluation test set. users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. xo vs. exter nal clock the ad 5930 can operate with master clocks up to 50 mhz. a 50 mhz oscillator is included on the evaluation board. however, this oscillator can be removed and, if required, an external cmos clock can be connected to the part. b
data sheet ad5930 rev. | page 25 of 28 schematic c35 0.1f c36 0.1f c34 0.1f c33 0.1f c32 0.1f c30 0.1f c28 0.1f 3.3v 3.3v t6 t7 t3 t4 t5 scl sda 1 reset pb0/fd0 pb1/fd1 3.3v pb2/fd2 pb3/fd3 pb4/fd4 pb5/fd5 pb6/fd6 pb7/fd7 pd0/fd8 pd1/fd9 pd2/fd10 pd3/fd 11 pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 ctl0/*flag a u4 cy7c68013-cs p ctl1/*flagb ctl2/*flagc sda scl xt alout xt alin 42 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52 29 30 31 16 15 4 5 44 54 9 8 33 34 35 36 37 38 39 40 1 2 13 14 6 12 10 26 28 41 53 56 3 11 7 17 27 32 43 55 *w akeu p clkout p a0/int0 st andb y p a1/int1 p a2/*sloe p a3/*wu2 p a4/fifoadr0 p a5/fifoadr1 p a6/*pktend p a7/*fld/slcs rdy0/*slrd rdy1/*s l wr ifclk agnd gnd gnd gnd gnd gnd gnd gnd a vcc vcc vcc vcc vcc vcc vcc vcc rsvd d? d+ 2 3 4 shield vbus d? d+ io gnd gnd 5 j1 u3 usb-mini-b 8 7 6 5 vcc wp scl sda a0 a1 a2 vss 24lc01 1 2 3 4 3.3v 3.3v c10 2.2f rt aj_ a c7 0.1f c0603 r17 0 r0603 r17 100k r0603 r3 1k r0603 led c4 0.1f c0603 c2 22pf c0603 y1 24mhz c1 22pf c0603 + + a 02 k 3.3v c12 0.1f c0603 3.3v c11 10f rt aj_ a c6 22pf c0603 + 1 2 6 3 vcc wp scl nr in1 in2 sd adp3303-3.3 8 7 5 4 3.3v 3.3v r1 2.2k r0603 r2 2.2k r0603 r4 100k r0603 c3 0.1f c0603 c8 0.1f c0603 c9 10f rt aj_ a 3.3v interrupt ctr l sdat a sclk fsync c5 0.1f c0603 ground link 1 gl2 2 05333-023 fig ure 40 . page 1 of eval - ad5930eb s chematic b
ad5930 data sheet rev. | page 26 of 28 ref ref j15 iout j11 c22 0.1f c0603 msbout msbout j10 c26 c0603 syncout syncout j9 c18 c0603 iout c24 c0603 r7 200 r0603 ioutb j12 ioutb t26 fs_a c25 c0603 r8 200 r0603 c21 c0603 r6 6.8k r0603 ground link sur f ace mount are a through hole are a u1 ad5930 gl1 16 + 11 7 18 6 5 4 15 14 fsync sclk sdat a 13 12 17 ctr l interrupt st andb y 1 2 3 fsadjust ref com p 19 20 iout ioutb 10 9 msbout syncout 8 mclk dgnd o/ p dgnd agnd cap/2.5v dvdd a vdd a vdd interrupt a vdd dvdd c23 0.01f c0603 c20 0.1f c0603 c19 10f rt aj_ a mclk + c15 0.1f c0603 lk7 c17 0.1f c0603 c37 0.1f c0603 c17 0.1f c0603 c16 10f rt aj_ a interrupt j7 int r11 10k r0603 lk5 a b ctr l ctr l j6 ctr l sdat a sclk fsync r10 10k r0603 fsync j3 sclk j4 sdat a j5 lk4 a b dvdd lk2 a b st andb y st andb y j8 st andb y r12 10k r0603 lk6 a b dvdd mclk j13 t25 t21 t22 r9 49.9k r0603 lk6 a b r15 r0603 u7 50mhz_x tal 14 7 vdd gnd o/ p 8 gnd en in adg774 4 7 9 12 d1 d2 d3 d4 s1a s2a s3a 2 5 11 s4a 14 3 1 15 8 6 10 13 s1b s2b s3b s4b t23 t24 vdd 16 fsync dvdd sclk sdat a dvdd r16 1.5k 21 a vdd a vdd j14?1 agnd j14?2 lk8 l1 bead b a 3.3v c31 0.1f c0603 c29 10f rt aj_ a dvdd dvdd j2?1 dgnd j2?2 lk1 a b c14 0.1f c0603 c13 10f rt aj_ a 05333-024 figure 41 . page 2 of eval - ad5930eb s chematic b
data sheet ad5930 rev. b | page 27 of 28 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 42. 20-lead thin shrink small outline package (tssop) (ru-20) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad5930yruz ?40c to +125c 20-lead thin shrink small outline package [tssop] ru-20 ad5930yruz-reel7 ?40c to +125c 20-lead thin shrink small outline package [tssop] ru-20 eval-ad5930ebz evaluation board 1 z = rohs compliant part.
ad5930 data sheet rev. b | page 28 of 28 notes ? 2005C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05333-0-7/12(b)

▲Up To Search▲

Price & Availability of AD5930-15

	To Download AD5930-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .